1. Technical Field
The present disclosure relates to a wiring substrate and a method of manufacturing the same.
2. Related Art
For example, when electrode pads are formed on a wiring substrate by a substructive method, a resist pattern having openings is formed on the surface of a copper foil, the copper foil exposed from the openings is etched, and the resist pattern is removed. Thus, electrode pads are formed of the remaining copper foil.
When electrode pads are formed on a wiring substrate by a semi-additive method, first of all, a seed layer is formed on an insulating layer at the outermost surface of the substrate by an electroless plating method, and a resist pattern having openings is formed on the surface of the seed layer. Next, electrode pads are formed on the seed layer exposed from the openings by electrolytic plating, the resist pattern is removed, and an unnecessary seed layer is removed by etching. Thus, electrode pads are formed of an electrolytic plated film.
As described above, the electrode pads can be formed on the wiring substrate by various methods. Meanwhile, the structure of a wiring substrate having electrode pads, in particular, the structure of a wiring substrate having electrode pads exposed from the insulating layer at the outermost surface of the substrate is described in JP-A-2005-327780, JP-A-2002-198462 and JP-A-2007-13092, for example.
JP-A-2005-327780 describes a wiring substrate for a semiconductor package in which all of lower wiring layers are located at positions where concave portions of a base insulating film are recessed. In this wiring substrate, an easy-to-etch layer on all of the lower wiring layers is removed, such that concave portions are formed.
JP-A-2002-198462 describes a wiring substrate for a semiconductor package in which a plurality of electrodes are exposed from the bottom of concave portions of an insulating layer. In this wiring substrate, all of the electrodes are etched and removed by a predetermined thickness from the lower surface of the wiring substrate.
JP-A-2007-13092 describes a wiring substrate in which a plurality of electrodes are recessed from the outer surface of a solder resist layer. In this wiring substrate, all of the electrodes are recessed by etching an electrode height adjusting layer on the electrodes.
FIG. 45 shows a semiconductor package including a wiring substrate 101, in which a plurality of electrode pads 102 are exposed from an insulating layer 103. In the wiring substrate 101 shown in FIG. 45, similarly to the wiring substrates described in JP-A-2005-327780, JP-A-2002-198462 and JP-A-2007-13092, mounting surfaces of a plurality of electrode pads 102 are exposed from concave portions 104 having the same depth formed in the insulating layer 103. The wiring substrate 101 includes a wiring layer 105 which forms external connection terminals, solder resist 106 which covers the wiring layer 105, and vias 107 which are formed in the solder resist 106 and electrically connect the electrode pads 102 and the wiring layer 105.
For example, when a semiconductor chip is mounted on the electrode pads 102 side of the wiring substrate 101, the electrode pads 102 and the external connection terminals (for example, electrode bumps) of the semiconductor chip are electrically connected to each other. In addition to the semiconductor chip, a heat sink (for example, a lid) for heat dissipation of the semiconductor chip, an additional wiring substrate, and electronic components, such as a chip capacitor, may be mounted on the wiring substrate 101.
Meanwhile, with high-function and reduction in size of semiconductor devices, there are demands for reduction in size and thickness of semiconductor packages (wiring substrate) on which a semiconductor chip is mounted, and for miniaturization and reduction in pitch of wiring layers or electrode pads. To meet such demands, when various components, such as a semiconductor chip, a heat sink, an additional wiring substrate, and electronic components, are mounted on the wiring substrate 101, the degree of freedom regarding mounting is low.
When various components, such as a semiconductor chip and a heat sink, are mounted on the wiring substrate 101, external connection terminals having different sizes of various components may be connected to a plurality of electrode pads 102 of the wiring substrate 101. In this case, the semiconductor chip, the heat sink, and the like are mounted on the wiring substrate 101 only by controlling the amount of a connection material, such as solder, which is used for the external connection terminals. For example, with regard to reduction in thickness of the semiconductor package, like the electrode pads 102 of the wiring substrate 101, when all of the mounting surfaces have the same depth from the outermost surface, it is necessary to adjust the connection height of various components by the amount of solder for mounting, such that the degree of freedom regarding mounting is low. For this reason, the amount of solder for connection differs between various components. Accordingly, it is difficult to adjust the amount of solder, and reliability of the connection portions is deteriorated.